The present invention relates to a semiconductor device having in a drift section a parallel p-n layer arranged with n-type semiconductor layers and p-type semiconductor layers being alternately joined and a method of manufacturing the semiconductor device having such an arrangement.
In general, semiconductor elements may be classified into lateral elements each having electrodes formed on its one side and vertical elements each having electrodes on both sides. In a vertical element, both of the direction in which a drift current flows in a turned-on state and the direction in which a depletion layer, formed by a reverse bias voltage, extends in a turned-off state are the same. In an ordinary planer n-channel vertical MOSFET (insulated gate field effect transistor), a high resistance drift layer is operated as a region for flowing a drift current in the vertical direction when the MOSFET is in a turned-on state. Therefore, a shortened current path in the drift layer lowers drift resistance, by which an effect of reducing substantial on-resistance of the MOSFET is obtained.
While, the drift layer is depleted when in a turned-off state to enhance a breakdown voltage. Therefore, the thinned drift region narrows the expanding width of a depletion layer between the drain and the base which layer travels from the p-n junction between a p-type base region and the n-type drift layer. This causes the electric field strength in the depletion layer to fast reach the critical electric field strength of silicon to lower the breakdown voltage. Contrary to this, in a semiconductor element with a high breakdown voltage, a thick drift layer increases on-resistance to result in an increase in a loss. In this way, between the on-resistance and the breakdown voltage, there is a relation that necessitates a tradeoff.
The tradeoff is known to be similarly necessary also in a semiconductor element such as an IGBT (insulated gate bipolar transistor), a bipolar transistor or a diode. Moreover, the same tradeoff is necessary also in a lateral semiconductor element in which the direction in which a drift current flows in a turned-on state differs from the direction in which a depletion layer extends in a turned-off state.
A well-known solving measure to the problem of necessitating the above-explained tradeoff is to provide a super-junction semiconductor element in which a drift layer is provided as a parallel p-n layer having a structure with n-type semiconductor layers and p-type semiconductor layers alternately joined, both having increased impurity concentrations. In the semiconductor device with such a structure, even though the impurity concentrations in the parallel pn-structure are high, when in a turned-off state, a depletion layer expands in the lateral direction from each p-n junction extending in the vertical direction of the parallel p-n layer. This makes the whole drift section depleted, by which a high breakdown voltage can be provided.
A previously known method of making a parallel p-n layer of a super-junction semiconductor device is a method of alternately carrying out epitaxial growth of the n-type semiconductor layer and selective ion implantation of p-type impurities (hereinafter referred to as a multistage epitaxial growth method). The method is disclosed in, for example, JP-A-2001-298190 and JP-A-2003-224273. Another method is proposed in JP-A-2001-196573, for example, in which a plurality of trenches are formed in an n-type semiconductor layer and each trench is filled with an epitaxial layer of p-type semiconductor (hereinafter referred to as a trench filling method).
In the trench filling method, the number of times of carrying out the epitaxial growth is smaller than that in the multistage epitaxial growth method. This provides the advantage of lowering cost. However, for ensuring a breakdown voltage of a super-junction semiconductor device manufactured by the trench filling method, a peripheral voltage withstanding structure, provided in an edge structure section, must be made different from the structure provided in the case when the super-junction semiconductor device is manufactured by the multistage epitaxial growth method. Here, the edge structure section is provided in the inactive region on the outside of the active region in which a current flows when the super-junction semiconductor device is in a turned-on state.
The reason will be explained in the following. Here, all of the MOSFETs are taken as those of n-channel type. Moreover, the parallel p-n layer is taken as a structure with a plane figure in which long narrow extended n-semiconductor layers and p-semiconductor layers are alternately joined in the direction perpendicular to the extending direction of the n-semiconductor layers (hereinafter referred to as a stripe-pattern-like plane figure). In the specification, the direction in which the n-semiconductor layer (or the p-semiconductor layer) in the parallel p-n layer are extended is taken as the direction parallel to the stripes in the parallel p-n layer. The direction orthogonal to this is taken as the direction perpendicular to the stripes in the parallel p-n layer.
Moreover, it is assumed that, in the inactive region, there are laid out a parallel p-n layer with a high impurity concentration like the parallel p-n layer in the active region. A section along a side extending in the direction perpendicular to the stripes of the parallel p-n layer in the edge structure section becomes a lateral super-junction structure when the MOSFET is in a turned-off state, which can ensure a sufficiently high breakdown voltage in the section. Meanwhile, in a section along a side extending in the direction parallel to the stripes of the parallel p-n layer in the edge structure section, a depletion layer tends to expand in the horizontal direction (lateral direction) from the p-n junctions when the MOSFET is in a turned-off state. The depletion layer, however, is not made to expand sufficiently because of high impurity concentration in the n-semiconductor layer in the parallel p-n layer laid out in the inactive region. Therefore, a sufficiently high breakdown voltage cannot be ensured in the edge structure section parallel to the stripes.
In order to avoid the problem, it is necessary to provide the structure of the parallel p-n layer in the edge structure section as a structure different from the structure of the parallel p-n layer in the active region. That is, the structure must be provided as a structure that reduces the electric field strength at least on the surface of the parallel p-n layer in the edge structure section to make a depletion layer expand easily in the edge structure section. Specifically, such a structure is disclosed in the above JP-A-2001-298190 as a structure in which, in the parallel p-n layer in the edge structure section, impurity concentration is lowered or the pitch of the stripes is narrowed. Furthermore, the impurity concentration is lowered together with the pitch of the stripes is narrowed or the impurity concentration is lowered together with the pitch of the stripes is increased. In the structure disclosed in the above JP-A-2001-298190, as shown in FIG. 47, in the parallel p-n layer in the active region, the amounts of impurities in the p-semiconductor layer and that in the n-semiconductor layer are equal to each other. Moreover, in the edge structure section, that is, in the parallel p-n layer in the inactive section, the amounts of impurities in the p-semiconductor layer and that in the n-semiconductor layer are also equal to each other.
In the above JP-A-2003-224273, a structure is disclosed in which the parallel p-n layer in the edge structure section is divided into two layers, an upper layer section and a lower layer section. In the structure, only in the parallel p-n layer in the upper layer section, impurity concentration is lowered or the pitch of the stripes is narrowed. Furthermore; the impurity concentration is lowered together with the pitch of the stripes is narrowed or the impurity concentration is lowered together with the pitch of the stripes is increased. The super-junction semiconductor devices disclosed in the above JP-A-2001-298190 and JP-A-2003-224273, are manufactured by the multistage epitaxial growth method. In the multistage epitaxial growth method, by changing a dose at selective ion implantation and/or a ratio of a window width at ion implantation, impurity concentration can be changed. Therefore, it is easy to lower only the impurity concentration in the parallel p-n layer in the edge structure section.
In general, for ensuring a stable breakdown voltage in a semiconductor device, a peripheral voltage withstanding structure must be provided. However, in the above JP-A-2001-196573 in which the trench filling method is proposed, no peripheral voltage withstanding structure and no method of manufacturing the structure are mentioned. Thus, the device according to the above JP-A-2001-196573 has a possibility of making it difficult to ensure a stable breakdown voltage. Therefore; the inventors studied the technique of forming the peripheral voltage withstanding structure as is disclosed in the above JP-A-2001-298190 by the trench filling method as is disclosed in the above JP-A-2001-196573. As a result, it was found that the widths of the p-semiconductor layers and the n-semiconductor layers in the parallel p-n layer can be controlled by changing the width of each of the trenches to be formed and spacing between the trenches (pitch). Specifically, it was found that, for ensuring the stable breakdown voltage, it is only necessary to make the widths and the pitch of the trenches in the inactive region smaller than the widths and the pitch of the trenches in the active region.
However, the trench widths in the inactive region made excessive small cause too low impurity concentrations in the p-semiconductor layers. This results in weakened effect of expanding the depletion layer outward the p-semiconductor layers. Therefore, the depletion layer expands poorly to cause inconvenience of making the breakdown voltage hard to be ensured. Moreover, trench widths made excessively small in the inactive region cause the trenches hard to be formed. Along with this, an aspect ratio of each of the trenches is made too high to cause difficulty in filling the trenches with epitaxial layers.
In addition, there was also studied the technology of forming the peripheral voltage withstanding structure as is disclosed in the above JP-A-2003-224273 by the trench filling method. In the disclosed structure, the parallel pn-structure in the edge structure section in the inactive region is divided into two layers of the upper layer section and the lower layer section. As a result, it was found that to change impurity concentration only in the p-semiconductor layer in the upper layer section or only in the n-semiconductor layer in the upper layer is impossible with one time formation of the trenches and one time epitaxial growth for filling the trenches. This is attributed to uniform distribution of the impurity concentration in the substrate before the trenches are formed therein and impurity concentration distribution becoming uniform when the trenches are filled.
The invention was made in view of the foregoing with an object of providing a semiconductor device being provided with a super-junction structure capable of ensuring a sufficiently high breakdown voltage. Another object of the invention is to provide a semiconductor device provided with a super-junction structure suited for being manufactured by a trench filling method. Further another object of the invention is to provide a method of manufacturing a semiconductor device provided with the super-junction structure by the trench filling method.